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preliminary user?s manual NU85E212 nu85e213 nu85e252 nu85e263 instruction cache, data cache nu85e, nu85et document no. a15241ej2v1um00 (2nd edition) date published january 2002 ns cp(n) 1991 ? printed in japan 2001
preliminary user?s manual a15241ej2v0um 2 [memo]
preliminary user?s manual a15241ej2v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary user ? s manual a15241ej2v0um 4 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
preliminary user?s manual a15241ej2v0um 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
preliminary user?s manual a15241ej2v0um 6 major revisions in this edition pages description p.27 addition of description to caution in 1.4.2 tag clear function p.28 addition of caution 2 in 1.4.2 tag clear function p.28 addition of description to caution and addition of remark 3 in 1.4.3 autofill function (way 0 only) p.29 addition of description to caution 2 in 1.5 instruction cache setting procedure p.30 addition of description to caution in 1.6.2 operation on instruction cache miss p.37 addition of 1.9 (9) simultaneous operation of refill read cycle and cache access by specific instruction that performs branch p.98 modification of example 1 in 2.10 (5) other the mark shows major revised points.
preliminary user?s manual a15241ej2v0um 7 preface target readers this manual is intended to give users an understanding the functions of the instruction caches (NU85E212 and nu85e213) and data caches (nu85e252 and nu85e263) for the nu85e and nu85et cpu cores for cbics in order to design application systems using these cpu cores. purpose this manual?s purpose is to help the user understand the functions of the instruction and data caches. organization this manual is organized as follows. chapter 1 instruction cache this chapter explains the NU85E212 and nu85e213, which are instruction caches. chapter 2 data cache this chapter explains the nu85e252 and nu85e263, which are data caches. how to use this manual this manual assumes that the reader has general knowledge of electrical engineering, logic circuits, and microcontrollers. to gain a general understanding of the functions of the instruction and data caches, refer to: this manual in the order of contents for information about the functions of the nu85e and nu85et, refer to: nu85e hardware user?s manual (a14874e) and nu85et hardware user?s manual (a15015e) in this manual, unless specifically noted, the nu85e is described as the typical cpu core product. when using the nu85et, read ?nu85e? as ?nu85et?. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxxz (z is appended to the pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ? xxxx or xxxxb decimal ? xxxx hexadecimal ? xxxxh prefix indicating the power of 2 (address space, memory capacity): k (kilo) ? 2 10 = 1,024 m (mega) ? 2 20 = 1,024 2 g (giga) ? 2 30 = 1,024 3 data types: word ? 32 bits halfword ? 16 bits byte ? 8 bits
preliminary user?s manual a15241ej2v0um 8 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? v850e1 architecture user?s manual (u14559e) ? nu85e hardware user?s manual (a14874e) ? nu85et hardware user?s manual (a15015e) ? memory controller nu85e, nu85et user?s manual (a15019e) ? cb-10 family vx type nu85e, nu85et design manual (a15401e) the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
preliminary user?s manual a15241ej2v0um 9 contents chapter 1 instruction cache................................................................................................... ......14 1.1 outline ................................................................................................................... ...........................14 1.1.1 features................................................................................................................ ................................14 1.1.2 symbol diagram .......................................................................................................... ..........................15 1.1.3 nu85e connection example ................................................................................................ .................16 1.2 pin functions ............................................................................................................. .....................17 1.2.1 list of pin functions ................................................................................................... ............................17 1.2.2 explanation of pin functions............................................................................................ ......................18 1.2.3 pin status .............................................................................................................. ................................20 1.3 configuration of instruction cache........................................................................................ .......21 1.3.1 4 kb 2-way set-associative instruction cache............................................................................ ...........22 1.3.2 8 kb 2-way set-associative instruction cache............................................................................ ...........23 1.4 instruction cache control functions....................................................................................... .....24 1.4.1 control registers....................................................................................................... .............................24 1.4.2 tag clear function ...................................................................................................... ...........................27 1.4.3 autofill function (way 0 only) .......................................................................................... .......................28 1.5 instruction cache setting procedure....................................................................................... .....29 1.6 operation ................................................................................................................. ........................29 1.6.1 operation on instruction cache hit ...................................................................................... ..................29 1.6.2 operation on instruction cache miss..................................................................................... ................30 1.7 bus cycle issued by instruction cache..................................................................................... ...31 1.8 refill sequence to instruction cache...................................................................................... ......34 1.9 cautions .................................................................................................................. .........................35 chapter 2 data cache .......................................................................................................... .............38 2.1 outline ................................................................................................................... ...........................38 2.1.1 features................................................................................................................ ................................38 2.1.2 symbol diagram .......................................................................................................... ..........................39 2.1.3 nu85e connection example ................................................................................................ .................40 2.2 pin functions ............................................................................................................. .....................41 2.2.1 list of pin functions ................................................................................................... ............................41 2.2.2 explanation of pin functions............................................................................................ ......................42 2.2.3 pin status .............................................................................................................. ................................46 2.3 configuration of data cache............................................................................................... ...........47 2.3.1 4 kb directly mapped data cache ......................................................................................... ................48 2.3.2 8 kb 2-way set-associative data cache ................................................................................... .............49 2.4 data cache control functions.............................................................................................. .........50 2.4.1 control registers....................................................................................................... .............................50 2.4.2 tag clear function ...................................................................................................... ...........................53 2.4.3 tag fill function....................................................................................................... ...............................53 2.4.4 lock function........................................................................................................... ..............................53 2.4.5 data flush function ..................................................................................................... ...........................54
preliminary user?s manual a15241ej2v0um 10 2.5 data cache setting procedure .............................................................................................. ........ 55 2.5.1 setting to validate data cache .......................................................................................... .................... 55 2.5.2 setting to validate, invalidate, and revalidate data cache .............................................................. ...... 55 2.6 operation................................................................................................................. ........................ 56 2.6.1 write through mode...................................................................................................... ........................ 57 2.6.2 writeback mode (write allocate disabled) ................................................................................ ............ 61 2.6.3 writeback mode (write allocate enabled) ................................................................................. ............ 66 2.7 bus cycles issued by data cache ........................................................................................... ..... 72 2.8 timing of refill from sdram to data cache ............................................................................... 90 2.9 refill sequence to data cache............................................................................................. ......... 94 2.10 cautions ................................................................................................................... ....................... 98
preliminary user?s manual a15241ej2v0um 11 list of figures (1/2) figure no. title page 1-1 nu85e and instruction cache connection example ............................................................................ ..........16 1-2 instruction cache configuration example ................................................................................... ...................21 1-3 configuration of 4 kb 2-way set-associative instruction cache ............................................................. ......22 1-4 configuration of 8 kb 2-way set-associative instruction cache ............................................................. ......23 1-5 instruction cache control register (icc) .................................................................................. .....................25 1-6 instruction cache data configuration register (icd)....................................................................... ..............26 1-7 operation on instruction cache hit........................................................................................ .........................29 1-8 operation on instruction cache miss....................................................................................... .......................30 1-9 sequential refill read cycle (4r) ......................................................................................... .........................32 1-10 refill sequence to instruction cache..................................................................................... .........................34 1-11 cache area setting example............................................................................................... ...........................36 2-1 nu85e and data cache connection example ................................................................................... ............40 2-2 data cache configuration example .......................................................................................... .....................47 2-3 configuration of 4 kb directly mapped data cache.......................................................................... .............48 2-4 configuration of 8 kb 2-way set-associative data cache .................................................................... ........49 2-5 data cache control register (dcc)......................................................................................... ......................51 2-6 data cache data configuration register (dcd) .............................................................................. ..............52 2-7 operation on data cache hit (write through mode, read) .................................................................... .......57 2-8 operation on data cache miss (write through mode, read) ................................................................... .....58 2-9 operation on data cache hit (write through mode, write) ................................................................... ........59 2-10 operation on data cache miss (write through mode, write) ................................................................. .......60 2-11 operation on data cache hit (writeback mode, write allocate disabled, read)...........................................61 2-12 operation on data cache miss (writeback mode, write allocate disabled, read, clean data)....................62 2-13 operation on data cache miss (writeback mode, write allocate disabled, read, dirty data)......................63 2-14 operation on data cache hit (writeback mode, write allocate disabled, write)...........................................64 2-15 operation on data cache miss (writeback mode, write allocate disabled, write)........................................65 2-16 operation on data cache hit (writeback mode, write allocate enabled, read) ...........................................66 2-17 operation on data cache miss (writeback mode, write allocate enabled, read, clean data) ....................67 2-18 operation on data cache miss (writeback mode, write allocate enabled, read, dirty data) ......................68 2-19 operation on data cache hit (writeback mode, write allocate enabled, write)............................................69 2-20 operation on data cache miss (writeback mode, write allocate enabled, write, clean data).....................70 2-21 operation on data cache miss (writeback mode, write allocate enabled, write, dirty data).......................71 2-22 sequential refill read cycle (4r) ........................................................................................ ..........................74
preliminary user?s manual a15241ej2v0um 12 list of figures (2/2) figure no. title page 2-23 critical first refill read cycle (2r-2r)................................................................................. ......................... 76 2-24 critical first refill read cycle (1r-2r-1r) .............................................................................. ...................... 78 2-25 sequential refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 4r) .... 82 2-26 critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 2r-2r) .......................................................................... .. 84 2-27 critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 1r-2r-1r)....................................................................... 86 2-28 refill timing example from sdram to data cache (sequential refill (4r), critical first refill (4r)) ........... 91 2-29 refill timing example from sdram to data cache (critical first refill (2r-2r)) ......................................... 92 2-30 refill timing example from sdram to data cache (critical first refill (1r-2r-1r)) ................................... 93 2-31 refill sequence to data cache (sequential refill (4r), critical first refill (4r))....................................... .... 94 2-32 refill sequence to data cache (critical first refill (2r-2r))............................................................ ............. 95 2-33 refill sequence to data cache (critical first refill (1r-2r-1r)) ......................................................... .......... 96
preliminary user?s manual a15241ej2v0um 13 list of tables table no. title page 1-1 pin status in each operating mode......................................................................................... .......................20 2-1 pin status in each operating mode......................................................................................... .......................46 2-2 list of operating modes................................................................................................... ...............................56 2-3 operating modes and bus cycles ............................................................................................ ......................73
preliminary user?s manual a15241ej2v0um 14 chapter 1 instruction cache 1.1 outline the NU85E212 and nu85e213 are instruction cache memories for the nu85e. they can be directly connected to the instruction cache interface incorporated in the nu85e. the following two types of instruction caches are available. ? NU85E212 ... 4 kb 2-way set-associative instruction cache (4 words 128 entries 2 ways = 4 kb) ? nu85e213 ... 8 kb 2-way set-associative instruction cache (4 words 256 entries 2 ways = 8 kb) 1.1.1 features ? use of least recently used (lru) algorithm this algorithm, which makes the block that has remained unaccessed the longest subject to replacement when a miss occurs, is used in the 2-way set-associative type cache. the probability of hitting is high compared to the directly mapped type. ? using the tag clear function, the contents of all tags can be cleared (invalidated). ? using the autofill function, instructions for one way can be filled automatically (way 0 only). a filled way is locked automatically, and replacing data in the way or writing to tags is disabled. thus, it can also be used as a rom that can operate in one cycle.
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 15 1.1.2 symbol diagram vpdw (15:0) out out out out out out out vpresz ibdrdy ibdle (3:0) ibedi (31:0) bcunch vpa (13:0) vpwrite vpubenz vpstb ifdrct ife128 vbclk iidrrq iiea (25:2) ibaack iircan iibtft in in in in in in in in in in in iiaack iidlef iiedi (31:0) iihit ibbtft ibdrrq ibea (25:2) vpdr (15:0) in in in in in in out in out vpdv bunriin in vptclk in
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 16 1.1.3 nu85e connection example the following figure shows an example of the connection of an instruction cache to the nu85e. figure 1-1. nu85e and instruction cache connection example nu85e ibbtft ibaack ibdrdy ibdle3 to ibdle0 ibedi31 to ibedi0 instruction cache (nu85e213) ibbtft ibaack ibdrdy ibdle3 to ibdle0 ibedi31 to ibedi0 ibea25 to ibea2 ibea25 to ibea2 ibdrrq ibdrrq iiaack iiaack iidlef iidlef iiedi31 to iiedi0 iiedi31 to iiedi0 iidrrq iidrrq iiea25 to iiea2 iiea25 to iiea2 iibtft iibtft iircan iircan bcunch bcunch ife128 ifdrct l l vbclk bunriin vbclk vbclk bunri bunri vpubenz vpubenz vpwrite vpwrite vpa13 to vpa0 vpa13 to vpa0 vpdr15 to vpdr0 vpdi15 to vpdi0 vpresz vpresz vpstb vpstb vptclk vptclk iihit open open l vpdw15 to vpdw0 vpdo15 to vpdo0 bunriout vpdv open
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 17 1.2 pin functions 1.2.1 list of pin functions pin name i/o function iibtft input input branch target fetch status from nu85e iircan input input code cancel status from nu85e iidrrq input input fetch request from nu85e iiea25 to iiea2 input input fetch address from nu85e iiaack output output address acknowledge to nu85e iidlef output output data latch enable to nu85e iiedi31 to iiedi0 output output data to nu85e ibaack input input address acknowledge from nu85e ibdrdy input input data ready from nu85e ibdle3 to ibdle0 input input data latch enable from nu85e ibedi31 to ibedi0 input input data from nu85e bcunch input input uncache status from nu85e ibea25 to ibea2 output output fetch address to nu85e ibbtft output nec reserved pin (leave open) ibdrrq output output fetch request to nu85e vpa13 to vpa0 input input address (for npb) vpwrite input input write access strobe (for npb) vpubenz input input higher byte enable (for npb) vpstb input input data strobe (for npb) vpdr15 to vpdr0 output output data (for npb) vpdw15 to vpdw0 input input data (for npb) vpresz input input reset vbclk input input internal system clock nu85e connection pins vpdv output output data bus direction control (for npb) ifdrct input nec reserved pin (input a low level) cache type selection pins ife128 input input entry selection status pin iihit output output tag hit status bunriin input input normal/test mode selection test mode pins vptclk input input clock for test remark npb: nec peripheral i/o bus
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 18 1.2.2 explanation of pin functions (1) nu85e connection pins (a) iibtft (input) iibtft inputs the branch target fetch status from the nu85e. a high level is input when fetching the target address on a branch instruction. (b) iircan (input) iircan inputs the code cancel status from the nu85e. this is the signal for canceling the preceding request when data becomes unnecessary due to a branch or interrupt after the nu85e outputs a fetch request to the instruction cache. (c) iidrrq (input) iidrrq inputs a fetch request from the nu85e. (d) iiea25 to iiea2 (input) iiea25 to iiea2 constitute a bus that inputs a fetch address from the nu85e. the address to be fetched is input from external memory at the same time as the fetch request (iidrrq). (e) iiaack (output) iiaack outputs an address acknowledge to the nu85e. this signal is output to the nu85e when a fetch address from the nu85e (iiea25 to iiea2) is recognized. (f) iidlef (output) iidlef outputs a data latch enable to the nu85e. (g) iiedi31 to iiedi0 (output) iiedi31 to iiedi0 constitute a bus that outputs data to the nu85e. this bus outputs the data that the nu85e is to read. (h) ibaack (input) ibaack inputs an address acknowledge from the nu85e. this signal is input when the nu85e recognizes the ibea25 to ibea2 signals output from the instruction cache. (i) ibdrdy (input) ibdrdy inputs a data ready from the nu85e. this is input when the nu85e is finished getting the data it was to read from external memory at the time of a miss, and indicates to the instruction cache that preparations for refill have been made. (j) ibdle3 to ibdle0 (input) ibdle3 to ibdle0 input a data latch enable from the nu85e. (k) ibedi31 to ibedi0 (input) ibedi31 to ibedi0 constitute a bus that inputs data from the nu85e. refill data is input from the nu85e when a miss occurs.
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 19 (l) bcunch (input) bcunch inputs the uncache status from the nu85e. a low level is input when an area for which the instruction cache setting was set to cacheable by the cache configuration register (bhc) of the nu85e is accessed. (m) ibea25 to ibea2 (output) ibea25 to ibea2 constitute a bus that outputs a fetch address to the nu85e. this bus outputs the address that the nu85e should read when a miss occurs. (n) ibbtft (output) ibbtft is reserved for nec. leave it open. fix the ibbtft pin of the nu85e to low level. (o) ibdrrq (output) ibdrrq outputs a fetch request to the nu85e. this pin outputs a signal requesting that the nu85e perform a fetch from external memory. (p) vpa13 to vpa0, vpwrite, vpubenz, vpstb (npb pins) refer to the nu85e hardware user?s manual (a14874e) . (q) vpdr15 to vpdr0 (output) vpdr15 to vpdr0 output data to the nu85e. connect these pins to the vpdi15 to vpdi0 pins of the nu85e. (r) vpdw15 to vpdw0 (input) vpdw15 to vpdw0 input data from the nu85e. connect these pins to the vpdo15 to vpdo0 pins of the nu85e. (s) vpresz (input) vpresz inputs a reset. (t) vbclk (input) vbclk inputs the internal system clock. (u) vpdv (output) vpdv outputs data bus direction control for the npb. when connecting to the nu85e, leave this pin open since it is not used. (2) cache type selection pins (a) ifdrct (input) ifdrct is reserved for nec. always input a low level. (b) ife128 (input) ife128 inputs the entry selection. entries are as follows depending on the level input to this pin. ? low level: 256 entries (fix nu85e213 to low level) ? high level: 128 entries (fix NU85E212 to high level)
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 20 (3) status pin (a) iihit (output) iihit indicates that the cache was hit. this pin outputs a high level on a hit. if not using this pin, leave it open. (4) test mode pins (a) bunriin (input) bunriin is an input pin that selects normal or test mode. connect this pin to the bunriout pin of the nu85e. (b) vptclk (input) vptclk inputs the clock for testing. 1.2.3 pin status the following table shows the status in each operating mode of the pins that have output functions. table 1-1. pin status in each operating mode pin status pin name reset stop mode halt mode test mode iiaack l maintained operating operating iidlef l maintained operating operating iiedi31 to iiedi0 undefined maintained operating operating ibea25 to ibea2 undefined maintained operating operating ibbtft l maintained operating operating ibdrrq l maintained operating operating vpdr15 to vpdr0 l maintained operating operating nu85e connection pins vpdv undefined maintained operating operating status pin iihit l maintained operating operating remark l: low-level output maintained: the previous status is maintained
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 21 1.3 configuration of instruction cache the following two types of instruction caches are available. the nu85e can be accessed by one of these instruction caches in one cycle. ? 4 kb 2-way set-associative instruction cache (NU85E212) ? 8 kb 2-way set-associative instruction cache (nu85e213) figure 1-2. instruction cache configuration example nu85e instruction cache interface bus control unit (bcu) external memory memory controller (memc) cpu instruction cache v850e system bus (vsb)
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 22 1.3.1 4 kb 2-way set-associative instruction cache the data memory of a 4 kb 2-way set-associative instruction cache has two ways, each consisting of a block of 128 entries of 4 words per line, for a total capacity of 4 kb. figure 1-3. configuration of 4 kb 2-way set-associative instruction cache ? ? ? ? ? ? index tag 30 1 2 10 11 25 ? ? ? ? ? ? tag part 128 entries data part (4 words) 2 7 15 internal bus ? ? ? ? ? ? 1 word 1 word 1 word 1 word internal bus comparator 15 15 32 32 selector instruction data ? ? ? ? ? ? 4 way selection control signal on hit iihit 32
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 23 1.3.2 8 kb 2-way set-associative instruction cache the data memory of an 8 kb 2-way set-associative instruction cache has two ways, each consisting of a block of 256 entries of 4 words per line, for a total capacity of 8 kb. figure 1-4. configuration of 8 kb 2-way set-associative instruction cache ? ? ? ? ? ? ? ? ? ? ? ? index tag 30 1 2 11 12 25 tag part 256 entries data part (4 words) 2 8 14 internal bus ? ? ? ? ? ? 1 word 1 word 1 word 1 word internal bus comparator 14 14 32 32 selector 4 ? ? ? ? ? ? way selection control signal on hit iihit instruction data 32
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 24 1.4 instruction cache control functions 1.4.1 control registers the following are the instruction cache control functions. ? tag clear function ? autofill function (way 0 only) these functions are controlled by the following registers. manipulatable bits address register name symbol r/w 1 bit 8 bits 16 bits initial value fffff070h instruction cache control register icc r/w ? ? 0003h note 1 fffff070h instruction cache control register l iccl r/w ? ? 03h note 2 fffff071h instruction cache control register h icch r/w ? ? 00h fffff074h instruction cache data configuration register icd r/w ? ? undefined notes 1. while reset is active, the value of this register becomes 0003h, and tag initialization begins automatically. upon completion of tag initialization, the value changes to 0000h. 2. while reset is active, the value of this register becomes 03h, and tag initialization begins automatically. upon completion of tag initialization, the value changes to 00h. remark the icc register and icd register are allocated in the peripheral i/o area of the nu85e. (1) instruction cache control register (icc) the icc register sets two types of functions: tag clear and autofill. the icc register can be read or written in 16-bit units. this register can be read or written in 8- or 1-bit units when the higher 8 bits of the icc register are used as the icch register and the lower 8 bits are used as the iccl register. cautions 1. if any of bits 0, 1, or 4 is set (1), do not forcibly clear (0) that bit. 2. do not set (1) bit 4 at the same time as the other bits. 3. do not set (1) bit 12. bit 12 can only be cleared (0). 4. make icc register settings using an uncacheable area (except for setting bit 4).
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 25 figure 1-5. instruction cache control register (icc) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 icc 000 lock 0 0000000 fill 0 00 tclr 1 tclr 0 address fffff070h initial value 0003h note bit position bit name description 12 lock0 this bit shows the cache lock status of way 0. when way 0 is filled, the cache is locked and this bit is set (1) automatically. clearing (0) this bit releases the cache lock of way 0. 0: way 0 is not locked 1: way 0 is locked 4 fill0 this bit sets way 0 autofill. setting (1) this bit autofills way 0. when autofill is complete, this bit is cleared (0) automatically. 0: way 0 fill complete 1: way 0 fill operating 1 tclr1 this bit sets way 1 tag clear. setting (1) this bit clears (invalidates) way 1 tags. when tag clear is complete, this bit is cleared (0) automatically. 0: way 1 tag clear complete 1: way 1 tag clear operating 0 tclr0 this bit sets way 0 tag clear. setting (1) this bit clears (invalidates) way 0 tags. when tag clear is complete, this bit is cleared (0) automatically. 0: way 0 tag clear complete 1: way 0 tag clear operating note while reset is active, the value of this register becomes 0003h, and tag initialization begins automatically. upon completion of tag initialization, the value changes to 0000h.
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 26 (2) instruction cache data configuration register (icd) the icd register sets the address of the memory area to be autofilled when using the autofill function. the icd register can be read or written in 16-bit units. cautions 1. do not overwrite the icd register while autofill is operating. 2. since the initial value of the icd register is undefined, when using the autofill function, be sure to set a value in the icd register prior to setting (1) the fill0 bit of the icc register. if the fill0 bit of the icc register is set (1) without setting a value in the icd register, the operation cannot be guaranteed. figure 1-6. instruction cache data configuration register (icd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 icd 0 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 address fffff074h initial value undefined bit position bit name description 14 to 1 data14 to data1 these bits set the higher 14 bits of the tag information (bits 25 to 12 of the start address of the memory area to be autofilled). 0 data0 NU85E212: this bit sets the lsb of the tag information (bit 11 of the start address of the memory area to be autofilled). nu85e213: be sure to set this bit to 0 (operation when 1 is set is not guaranteed).
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 27 1.4.2 tag clear function the tag clear function clears (invalidates) the tags of one way. in addition, it automatically clears (invalidates) the tags of all ways on a reset. use the following procedure to perform instruction cache tag clear. <1> read the instruction cache control register (icc) and confirm that bits 0 and 1 (tclr0, tclr1) are all cleared (0). <2> read the icc register and confirm that bit 12 (lock0) is cleared (0). bit 13 of the icc register is always cleared (0). <3> set the tclr0 and tclr1 bits of the icc register as follows. caution perform all of <1> to <3> above (tag clear) using an uncacheable area (tags are not cleared if the above processing is performed in a cacheable area). ? ? ? ? when clearing way 0 and way 1 at the same time: (a) set (1) the tclr0 and tclr1 bits. (b) read the tclr0 and tclr1 bits to confirm that these bits are cleared (0). ? ? ? ? when clearing way 0 and way 1 individually note : (a) set (1) the tclr0 bit. (b) read the tclr0 bit to confirm that this bit is cleared (0). (c) set (1) the tclr1 bit. (d) read the tclr1 bit to confirm that this bit is cleared (0). note the setting can also be made in order of (c)-(d)-(a)-(b). cautions 1. way 0 shares the counter to clear tags with way 1. thus, clear tags (set (1) the tclr0 bit or tclr1 bit of the icc register) when the counter for tag clearing is stopped (tclr0 = = = = tclr1 = = = = 0). when clearing the tags of way 0 and way 1 individually, if tag clearing for either way is executed during tag clear execution for the other way (tclr0 or tclr1 = = = = 1), the counter stops in the middle of tag clearing. consequently, normal tag clearing cannot be performed because the counter switches to perform the other tag clear operation still indicating the value it had when stopped halfway. be sure to confirm that tag clearing for one way is completed (tclr0 or tclr1 = = = = 0) before performing tag clearing for the other way. when setting both bits at the same time as shown below, there is no problem. mov 0x3, r2 lop0: id.h icc[r0], r1 cmp r0, r1 bnz lop0 st.h r2, icc[r0] lop1: id.h icc[r0], r1 cmp r0, r1 bnz lop1
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 28 cautions 2. be sure not to perform other processing simultaneously with tag clearing before reading the tclr0 and tclr1 bits of the icc register and confirming that these bits are cleared (0). remark the clock count required for a tag clear operation is shown below. ? NU85E212: 128 clocks ? nu85e213: 256 clocks 1.4.3 autofill function (way 0 only) the autofill function automatically fills instructions for one way. once autofilled, a way is automatically locked and write disabled and it operates the same as rom that is accessible in one cycle. when the lock is released, it again operates as an instruction cache. use the following procedure to perform instruction cache autofill. <1> clear (invalidate) the tags of way 0 (see 1.4.2 tag clear function ). <2> set the tag information corresponding to the memory area to be autofilled in the instruction cache data configuration register (icd). <3> branch to the cacheable area corresponding to the tag information set in the icd register. <4> set (1) bit 4 (fill0) of the instruction cache control register (icc). <5> when autofill is complete, bit 12 (lock0) of the icc register is automatically set (1) and the way 0 is locked. at that same time, read bit fill0 of the icc register and confirm that that bit is cleared (0). caution perform the above operations in the areas shown below. <1>, <2>, <3> ..... uncacheable area <4> ..................... cacheable area if bit 4 (fill0) of the icc register is set (1) using an uncacheable area, autofill cannot be performed (invalid operation). <5> ..................... either a cacheable area or an uncacheable area is fine remarks 1. a lock is released by clearing (0) bit lock0 of the icc register. 2. the number of clocks required for a 1-way autofill is as follows (when the vsb wait count is 0, vsb data bus size is 32 bits, and 32-bit (1 word) data is filled in 1 clock). ? NU85E212: 512 clocks ? nu85e213: 1024 clocks 3. since autofill is performed from the external memory to the instruction cache via the vsb, other processing can be performed at the same time, but only if the processing involves operations within the cpu (processing without any vsb and npb accesses).
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 29 1.5 instruction cache setting procedure the instruction cache settings are performed using the following procedure with the initial settings of the user program immediately following system reset. <1> wait until the icc register value becomes ?0000h? (that is, tag initialization is completed). <2> make the instruction cache setting of the bhc register of the nu85e ?cacheable?. cautions 1. always input a low level to the ifiunch0 pin of the nu85e (instruction cache enable). if a low level is not input to the ifiunch0 pin, the ?cacheable? setting in the bhc register is invalid even if made. 2. be sure to make the bhc register settings using an uncacheable area (an instruction is not correctly fetched if settings are made using a cacheable area). 1.6 operation the instruction cache automatically performs a caching operation whenever there is a fetch access to a cacheable area set using the cache configuration register (bhc) of the nu85e. 1.6.1 operation on instruction cache hit <1> on a fetch access from external memory, output the fetch request (iidrrq) and address (iiea25 to iiea2) to the instruction cache. <2> if a hit occurs due to the address existing in the instruction cache, read the data by passing through iiedi31 to iiedi0 from the instruction cache. figure 1-7. operation on instruction cache hit cpu instruction cache interface instruction cache <1> nu85e <2> iiedi31 to iiedi0 iidrrq, iiea25 to iiea2
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 30 1.6.2 operation on instruction cache miss <1> on a fetch access from external memory, output the fetch request (iidrrq) and address (iiea25 to iiea2) to the instruction cache. <2> if a miss occurs due to the address not existing in the instruction cache, output a fetch request (ibdrrq) and the address to be read (ibea25 to ibea2) from the instruction cache to the bcu. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) to external memory via the vsb and refills the instruction cache with one line (4 words) at the address to be read. <4> the instruction cache then transfers the required data among the 4 words of refill data to the cpu by passing through iiedi31 to iiedi0. caution the miss penalty time when a miss occurs is the time required to refill 4-word data, and it varies depending on such things as memory controller (memc) specifications for external memory, memory type, bus width, and vsb bus cycle wait insertion time. figure 1-8. operation on instruction cache miss external memory cpu instruction cache interface instruction cache vsb <1> nu85e <2> <3> iidrrq, iiea25 to iiea2 ibdrrq, ibea25 to ibea2 vbdi31 to vbdi0 vma27 to vma0 ibedi31 to ibedi0 memc <4> iiedi31 to iiedi0 <3> bcu <3>
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 31 1.7 bus cycle issued by instruction cache the instruction cache issues a 4-word burst read (4r) sequential refill read cycle. figure 1-9 shows timing examples in the case of a 32-bit data bus and a 16-bit data bus. the bus cycle indicated in figure 1-9 (a) 32-bit data bus is 4 times greater when an 8-bit data bus is used as a result of bus sizing. remarks 1. the timing example is when no waits are used. 2. all signals in the timing example are nu85e signals. 3. the circles indicate the sampling timing. 4. for details of the vsb signals (vmxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) . 5. : undetermined state (for output), or arbitrary level (for input)
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 32 figure 1-9. sequential refill read cycle (4r) (1/2) (a) 32-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) (1,1) vmstz (output) adrs.+0h adrs.+4h adrs.+8h adrs.+ch (1,0) vmctyp2 to vmctyp0 (output) (0,0,0) vmbstr (output) vmbenz3 to vmbenz0 (output) (0,0,0,0) vmseq2 to vmseq0 (output) (0,1,0) (0,0,1) (0,0,0) vmlock (output) data.0 data.1 vmlast (input) vmahld (input) read data.2 data.3 vbdo31 to vbdo0 (output) l
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 33 figure 1-9. sequential refill read cycle (4r) (2/2) (b) 16-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) vmstz (output) adrs.+0h adrs.+2h adrs.+4h adrs.+6h vmctyp2 to vmctyp0 (output) vmbstr(output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) (0,1,1) (0,0,0) vmlock (output) data.7 vmlast (input) vmahld (input) read adrs.+8h adrs.+ah adrs.+ch adrs.+eh data.6 (0,0,1) (1,1,0,0) (0,0,0) (1,0) (1,1) data.5 data.4 data.3 data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 34 1.8 refill sequence to instruction cache figure 1-10 shows the refill sequence to the data part of an instruction cache when a miss occurs. figure 1-10. refill sequence to instruction cache (a) 32-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word higher address lower address data part (4 words) 128/256 entries <1> (adrs.+0h) <3> (adrs.+8h) <2> (adrs.+4h) <4> (adrs.+ch) (b) 16-bit data bus <8> (adrs.+eh) <7> (adrs.+ch) <6> (adrs.+ah) <5> (adrs.+8h) <4> (adrs.+6h) <3> (adrs.+4h) <2> (adrs.+2h) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 128/256 entries <1> (adrs.+0h) higher address lower address (c) 8-bit data bus <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <5> <6> <3> <4> <1> <2> ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 128/256 entries higher address lower address (adrs.+fh) (adrs.+eh) (adrs.+dh) (adrs.+ch) (adrs.+ah) (adrs.+6h) (adrs.+8h) (adrs.+4h) (adrs.+2h) (adrs.+0h) (adrs.+7h) (adrs.+9h) (adrs.+bh) (adrs.+5h) (adrs.+3h) (adrs.+1h) remarks 1. the numbers within pointed brackets (< >) indicate the refill sequence. 2. (adrs.+n): data of address in ( ) (n = 0h to fh)
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 35 1.9 cautions (1) connection to nu85e connect pins that have the same pin names. however, leave the ibbtft pin of the instruction cache open and fix the ibbtft pin of the nu85e to low level. the following pins should be connected as follows (connect to pins that do not have the same pin names). vpdr15 to vpdr0: connect to the vpdi15 to vpdi0 pins of the nu85e. vpdw15 to vpdw0: connect to the vpdo15 to vpdo0 pins of the nu85e. bunriin: connect to the bunriout pin of the nu85e. (2) setting cache type selection pins input the levels shown below to cache type selection pins beginning with if. input level pin name NU85E212 nu85e213 ife128 high level low level ifdrct low level low level (3) bus cycle status for an area for which the instruction cache setting was set to cacheable by the cache configuration register (bhc) of the nu85e, the vmctyp2 to vmctyp0 signals of the nu85e always indicate a normal opcode fetch and do not indicate an opcode fetch of the destination address for a branch instruction. (4) operation on reset at the time of a reset, tags are automatically cleared (invalidated), which puts the next data replacement in a state of being performed from way 0. therefore, if there is an access to the instruction cache within a period of as many clock cycles as the number of lines after a reset, the cpu stops until the tags are cleared (become invalid). (5) setting registers be sure to set the nu85e registers shown below using an uncacheable area. however, set bit 4 of the instruction cache control register (icc) using a cacheable area. ? chip area select control registers (csc0, csc1) ? peripheral i/o area select control register (bpc) ? bus size configuration register (bsc) ? endian configuration register (bec) ? cache configuration register (bhc) ? instruction cache control register (icc) note ? instruction cache data configuration register (icd) note excluding bit 4
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 36 (6) access to memory boundary if adjacent chip select (csn) areas are a cacheable area and an uncacheable area, continuous access across the memory boundary is possible only by using a branch instruction (n = 7 to 0). operation is not guaranteed if the memory boundary is continuously accessed by an instruction other than a branch instruction. an example is shown below. example suppose that cache area settings are as shown in figure 1-11. in this case, access to the memory areas is as follows. ? from cs0 area to cs1 area, access is possible only by using a branch instruction. ? from cs1 area to cs2 area, continuous access is possible. figure 1-11. cache area setting example (7) setting bhc register of nu85e in the case of csn areas for which an instruction to set the bhc register exists, cache enable/disable settings for the instruction cache using this instruction cannot be performed (n = 7 to 0). instruction cache enable/disable settings are possible only for csn areas for which no instruction for setting the bhc register exists. for example, if a bhc register setting instruction exists in the cs0 area, the instruction cache of the cs0 area cannot be set (cache enable/disable settings). in this case, only the instruction cache settings for areas cs1 to cs7 are possible. however, instruction cache settings for all csn areas from instructions that exist in memory areas connected to vfb or vdb are possible. remark vfb: dedicated bus used to directly connect rom (v850e fetch bus) vdb: dedicated bus used to directly connect ram (v850e data bus) cs0 area cs1 area cs2 area uncacheable area cacheable areas
chapter 1 instruction cache preliminary user?s manual a15241ej2v0um 37 (8) tag clear procedure way 0 shares the counter to clear tags with way 1. thus, clear tags (set (1) the tclr0 bit or tclr1 bit of the icc register) when the counter for tag clearing is stopped (tclr0 = tclr1 = 0). when clearing the tags of way 0 and way 1 individually, if tag clearing for either way is executed during tag clear execution for the other way (tclr0 or tclr1 = 1), the counter stops in the middle of tag clearing. consequently, normal tag clearing cannot be performed because the counter switches to perform the other tag clear operation still indicating the value it had when stopped halfway. be sure to confirm that tag clearing for one way is completed (tclr0 or tclr1 = 0) before performing tag clearing for the other way. (9) simultaneous operation of refill read cycle and cache access by specific instruction that performs branch in the nu85e instruction cache, an instruction that is read in the bus cycle in which the refill read cycle is started may be discarded without being registered in the instruction cache (even if this operation occurs, program execution itself is performed normally and the execution result is correct). this operation may occur when all the following conditions (a) to (c) are satisfied (even if all the following conditions are satisfied, however, this operation may not always occur since this operation occurs only when multiple conditions such as the internal status of the instruction cache or instruction execution timing are satisfied at the same time). (a) when the instruction of a cache line (16 bytes) in the instruction cache is being executed by the cpu (b) when the cache lines of the address following the above cache line do not exist in the instruction cache, and a miss occurs due to accessing the following cache lines by an instruction prefetch of the cpu (c) when a specific instruction note in the cache line that performs branch operation is executed by the cpu, and access to the branch destination is requested for the instruction cache at the same time as the above miss occurrence, and then the branch destination generates a hit in the instruction cache note the target instructions are as follows. bcond, callt, ctret, dbret, dbtrap, jarl, jmp, jr, reti, switch, trap, dispose imm5, list12[reg1] (instruction with branch to [reg1]) when this operation occurs, the refill read cycle is started due to a miss occurrence in the following cache lines. the instructions that are read in that cycle are discarded without being registered in the instruction cache. this may lower the performance of program execution. for example, if this operation occurs due to the conditional branch instruction of the program loop block, the performance is lowered because the invalid refill read cycle of the following cache line occurs on every loop. especially, if the loop is small, the performance deterioration by the invalid bus cycle is larger. to avoid occurrence of this operation, allocate the branch instruction to the 6-byte area at the start of the cache line (16-byte boundary). this prevents the occurrence conditions ((a) to (c)) being satisfied, and so this operation does not occur.
preliminary user?s manual a15241ej2v0um 38 chapter 2 data cache 2.1 outline the nu85e252 and nu85e263 are data cache memories for the nu85e. they can be directly connected to the data cache interface incorporated in the nu85e. the following two types of data cache are available. ? nu85e252 ... 4 kb directly mapped data cache (4 words 256 entries = 4 kb) ? nu85e263 ... 8 kb 2-way set-associative data cache (4 words 256 entries 2 ways = 8 kb) 2.1.1 features ? use of least recently used (lru) algorithm this algorithm, which makes the block that has remained unaccessed the longest subject to replacement when a miss occurs, is used in the 2-way set-associative type cache. the probability of hitting is high compared to the directly mapped type. ? using the tag clear function, the contents of all tags can be cleared (invalidated). ? using the tag fill function, the contents of all tags can be filled with addresses of memory to be filled. by locking a filled way, it also can be used as data ram. however, the dma operation of the nu85e cannot be performed by using a locked data ram. ? using the lock function, any way can be locked. writing to a tag of a locked way is disabled. ? using the data flush function, dirty data lines can be flushed in writeback mode. remark dirty data is data in the cache memory that must be written back to the main memory if data of the same address in the cache memory and main memory is different. in contrast, if data of the same address in the cache memory and main memory is the same, the data in the cache memory is called clean data.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 39 2.1.2 symbol diagram note this pin is only in the nu85e263. it is not in the nu85e252. in/out out out out in out out vpresz iramrwb iramwr (3:0) irrsa iramwt vpa (13:0) vpwrite vpubenz vpstb ifiaseq ifirabe vbclk iddarq idunch ides iraoz (31:0) irama (27:2) in in in out in in in in in in in iramz (31:0) idrrdy idhum idhit idretr idea (27:0) ided (31:0) iddrrq bunriin in vptclk in in in in in in in out vpdw (15:0) in ifidrct note in out iddwrq out idseq4 out idseq2 in idaack in iddrdy out ifiunch1 out ifiwrth vpdr (15:0) out out vpdv
chapter 2 data cache preliminary user?s manual a15241ej2v0um 40 nu85e idaack idaack iddarq iddarq iddrrq iddrrq iddrdy iddrdy iddwrq iddwrq idea27 to idea0 idea27 to idea0 ided31 to ided0 ided31 to ided0 ides ides irrsa irrsa idhum idhum idretr idretr idrrdy idrrdy idseq2 idseq2 idseq4 idseq4 data cache (nu85e263) iramz31 to iramz0 iramwr3 to iramwr0 iramwr3 to iramwr0 iraoz31 to iraoz0 iraoz31 to iraoz0 irama27 to irama2 irama27 to irama2 iramz31 to iramz0 iramrwb iramrwb vpa13 to vpa0 vpdi15 to vpdi0 vpresz vpstb vptclk vpubenz vpwrite ifirabe ifirabe ifiaseq ifidrct l idhit arbitrary l open vpubenz vpwrite vpa13 to vpa0 vpresz vpstb vptclk iramwt iramwt idunch idunch vbclk bunriin vbclk vbclk bunri bunri ifiunch1 ifiunch1 ifiwrth ifiwrth l vpdo15 to vpdo0 vpdw15 to vpdw0 vpdr15 to vpdr0 bunriout vpdv open caution since the v850e data bus (vdb) is used to connect the data cache to the nu85e, ram and the data cache cannot be used at the same time. connect either ram or the data cache to the vdb. 2.1.3 nu85e connection example the following figure shows an example of the connection of a data cache to the nu85e. figure 2-1. nu85e and data cache connection example
chapter 2 data cache preliminary user?s manual a15241ej2v0um 41 2.2 pin functions 2.2.1 list of pin functions (1/2) pin name i/o function irama27 to irama2 input input address from nu85e iraoz31 to iraoz0 input input data from nu85e iddarq input input read/write access request from nu85e idunch input input uncache status ides input nec reserved pin (connect to ides pin of nu85e) iramrwb input input read/write status from nu85e iramwr3 to iramwr0 input input write enable from nu85e irrsa input input vdb hold status iramwt output output wait to nu85e iramz31 to iramz0 output output data to nu85e idrrdy output output read data ready to nu85e idhum output output hit under miss read idretr input input read retry request idea27 to idea0 output output address ided31 to ided0 i/o input and output data iddrrq output output vsb read operation request to nu85e iddwrq output output vsb write operation request to nu85e idseq4 output output read or write operation type setting idseq2 output output read or write operation type setting idaack input input acknowledge iddrdy input input read data ready from nu85e ifiunch1 output output data cache setting to nu85e ifiwrth output output writeback or write through mode selection vpa13 to vpa0 input input address (for npb) vpwrite input input write access strobe (for npb) vpubenz input input higher byte enable (for npb) vpstb input input data strobe (for npb) vpdw15 to vpdw0 input input data (for npb) vpdr15 to vpdr0 output output data (for npb) vpdv output output data bus direction control (for npb) vpresz input input reset nu85e connection pins vbclk input input internal system clock remark vdb: v850e data bus vsb: v850e system bus npb: nec peripheral i/o bus
chapter 2 data cache preliminary user?s manual a15241ej2v0um 42 (2/2) pin name i/o function ifiaseq input input refill mode selection ifirabe input nec reserved pin (input a low level) cache type selection pins ifidrct note input nec reserved pin (input a low level) status pin idhit output output tag hit status bunriin input input normal/test mode selection test mode pins vptclk input input clock for test note this pin is only in the nu85e263. it is not in the nu85e252. 2.2.2 explanation of pin functions (1) nu85e connection pins (a) irama27 to irama2 (input) irama27 to irama2 constitute a bus that inputs an address from the nu85e. (b) iraoz31 to iraoz0 (input) iraoz31 to iraoz0 constitute a bus that inputs data from the nu85e. (c) iddarq (input) iddarq inputs a read or write access request from the nu85e. (d) idunch (input) idunch inputs the uncache status. a low level is input when an area for which the data cache setting was set to cacheable by the cache configuration register (bhc) of the nu85e is accessed. (e) ides (input) ides is reserved for nec. be sure to connect it to the ides pin of the nu85e. (f) iramrwb (input) iramrwb inputs read or write status from the nu85e. the read or write status of the data cache is as follows depending on the input level at this pin. ? low level: write ? high level: read
chapter 2 data cache preliminary user?s manual a15241ej2v0um 43 (g) iramwr3 to iramwr0 (input) iramwr3 to iramwr0 input a write enable from the nu85e. these pins indicate the valid byte data in the data bus (iraoz31 to iraoz0). a high level is input when byte data is valid. high level signal valid byte data iramwr0 iraoz7 to iraoz0 iramwr1 iraoz15 to iraoz8 iramwr2 iraoz23 to iraoz16 iramwr3 iraoz31 to iraoz24 (h) irrsa (input) irrsa inputs the v850e data bus (vdb) hold status. a high level is input if the vdb is in a ram access or hold status. (i) iramwt (output) iramwt outputs a wait to the nu85e. this pin outputs high level during the wait interval. (j) iramz31 to iramz0 (output) iramz31 to iramz0 constitute a bus that outputs data to the nu85e. (k) idrrdy (output) idrrdy outputs a read data ready to the nu85e. (l) idhum (output) idhum outputs a hit under miss read. the next access to the data cache is performed during access to external memory upon occurrence of a miss during read, and if the data hit on that access is input to the nu85e prior to data from external memory (hit under miss), a high level is output. (m) idretr (input) idretr inputs a read retry request. (n) idea27 to idea0 (output) idea27 to idea0 constitute a bus that outputs an address to the nu85e. this bus outputs the address the nu85e should access when a miss occurs. (o) ided31 to ided0 (i/o) ided31 to ided0 constitute a bus that inputs and outputs data from and to the nu85e. this bus passes data refilled in the data cache and data to write to external memory when in writeback mode.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 44 (p) iddrrq, iddwrq, idseq4, and idseq2 (output) iddrrq, iddwrq, idseq4, and idseq2 output operation type settings to the nu85e. iddrrq iddwrq idseq4 idseq2 operation type 1 0 1 0 4-word sequential read 1 0 0 1 2-word sequential read 1 0 0 0 1-word read 0 1 1 0 4-word sequential write 0 1 0 1 2-word sequential write 0 1 0 0 1-word write 1 1 1 1 1-word write 1 1 1 0 1-halfword write 1 1 0 0 1-byte write other than above setting prohibited remark 0: low-level output 1: high-level output (i) iddrrq (output) iddrrq outputs a vsb read operation request to the nu85e. (ii) iddwrq (output) iddwrq outputs a vsb write operation request to the nu85e. (iii) idseq4, idseq2 (output) idseq4 and idseq2 output read and write operation type settings to the nu85e. (q) idaack (input) idaack inputs an acknowledge. this signal is input when the nu85e recognizes idea27 to idea0 signals output from the data cache. (r) iddrdy (input) iddrdy inputs a read data ready from the nu85e. this is input when the nu85e is finished getting the data it was to read from external memory at the time of a miss, and indicates to the data cache that preparations for refill have been made. (s) ifiunch1 (output) ifiunch1 outputs the data cache setting to the nu85e. this pin outputs a low level when the data cache is enabled and a high level when the data cache is disabled (both the dc11 and dc10 bits of the dcc register are cleared (0)). ifiunch1 must be connected to ifiunch1 in the nu85e. (t) ifiwrth (output) ifiwrth outputs the writeback/write through mode selection. this pin outputs a low level for writeback mode and a high level for write through mode.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 45 (u) vpa13 to vpa0, vpwrite, vpubenz, vpstb (npb pins) refer to the nu85e hardware user?s manual (a14874e) . (v) vpdr15 to vpdr0 (output) vpdr15 to vpdr0 output data to the nu85e. connect these pins to the vpdi15 to vpdi0 pins of the nu85e. (w) vpdw15 to vpdw0 (input) vpdw15 to vpdw0 input data from the nu85e. connect these pins to the vpdo15 to vpdo0 pins of the nu85e. (x) vpdv (output) vpdv outputs data bus direction control for the npb. when connecting to the nu85e, leave this pin open since it is not used. (y) vpresz (input) vpresz inputs a reset. (z) vbclk (input) vbclk inputs the internal system clock. (2) cache type selection pins (a) ifiaseq (input) ifiaseq inputs the refill mode selection. the refill modes are as follows depending on the level input to this pin. ? low level: critical first mode ? high level: sequential mode remark critical first mode is a technique of taking the data needed first when taking a line of data from external memory. because the data is passed quickly to the cpu, overall system performance generally improves when operating in critical first mode. however, when memory that can be continuously accessed is connected, performance may be better if sequential mode is set. (b) ifirabe, ifidrct (input) ifirabe, ifidrct, and ifioect are reserved for nec. always input a low level. the ifidrct pin is only in the nu85e263. it is not in the nu85e252. (3) status pin (a) idhit (output) idhit indicates that the cache was hit. when data is hit during read from data cache, a high level is output. during write, the status is not indicated. leave this pin open when not used.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 46 (4) test mode pins (a) bunriin (input) bunriin is an input pin that selects normal or test mode. connect to the bunriout pin of the nu85e. (b) vptclk (input) vptclk inputs the clock for testing. 2.2.3 pin status the following table shows the status in each operating mode of the pins that have output functions. table 2-1. pin status in each operating mode pin status pin name reset stop mode halt mode test mode iramwt undefined maintained operating operating iramz31 to iramz0 undefined maintained operating operating idrrdy undefined maintained operating operating idhum undefined maintained operating operating idea27 to idea0 undefined maintained operating operating ided31 to ided0 undefined maintained operating operating iddrrq undefined maintained operating operating iddwrq undefined maintained operating operating idseq4 undefined maintained operating operating idseq2 undefined maintained operating operating ifiunch1 h maintained operating operating ifiwrth h maintained operating operating vpdr15 to vpdr0 l maintained operating operating nu85e connection pins vpdv undefined maintained operating operating status pin idhit undefined maintained operating operating remark h: high-level output l: low-level output maintained: the previous status is maintained
chapter 2 data cache preliminary user?s manual a15241ej2v0um 47 2.3 configuration of data cache the following two types of data caches are available. the nu85e can be accessed by one of these data caches in one cycle. ? 4 kb directly mapped data cache (nu85e252) ? 8 kb 2-way set-associative data cache (nu85e263) figure 2-2. data cache configuration example nu85e external memory memory controller (memc) cpu data cache interface bus control unit (bcu) data cache dma control unit (dmac) v850e system bus (vsb)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 48 2.3.1 4 kb directly mapped data cache the data memory of a 4 kb directly mapped data cache, which consists of a block of 256 entries of 4 words per line, has a total capacity of 4 kb. figure 2-3. configuration of 4 kb directly mapped data cache index tag 30 1 2 11 12 27 tag part 256 entries data part (4 words) 2 8 16 internal bus ? ? ? ? ? ? 1 word 1 word 1 word 1 word comparator 16 32 data ? ? ? ? ? ? 4 idhit
chapter 2 data cache preliminary user?s manual a15241ej2v0um 49 2.3.2 8 kb 2-way set-associative data cache the data memory of an 8 kb 2-way set-associative data cache has 2 ways, each consisting of a block of 256 entries of 4 words per line, for a total capacity of 8 kb. figure 2-4. configuration of 8 kb 2-way set-associative data cache ? ? ? ? ? ? ? ? ? ? ? ? index tag 30 1 2 11 12 27 tag part 256 entries data part (4 words) 2 8 16 internal bus comparator 16 16 32 32 selector 4 ? ? ? ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word internal bus 32 way selection control signal on hit idhit data
chapter 2 data cache preliminary user?s manual a15241ej2v0um 50 2.4 data cache control functions 2.4.1 control registers the following are the data cache control functions. ? tag clear function ? tag fill function ? lock function ? data flush function these functions are controlled by the following registers. manipulatable bits address register name symbol r/w 1 bit 8 bits 16 bits initial value fffff078h data cache control register dcc r/w ? ? 0003h note fffff07ch data cache data configuration register dcd r/w ? ? undefined note while reset is active, the value of this register becomes 0003h, and tag initialization begins automatically. upon completion of tag initialization, the value changes to 0000h. remark the dcc register and dcd register are allocated in the peripheral i/o area of the nu85e. (1) data cache control register (dcc) the dcc register sets four types of functions: tag clear, tag fill, lock, and data flush. in addition, three operating modes can be selected using dcc register settings. the dcc register can be read or written in 16-bit units. cautions 1. if any of bits 0, 1, 4, or 5 is set (1), do not forcibly clear (0) that bit. 2. settings in bits 1, 5, and 13 are valid only for the nu85e263. be sure to set these bits to 0 in the nu85e252. 3. be sure to set the data cache enable area (using the nu85e?s cache configuration register (bhc)) after setting the operation mode with the dcc register. failure to do this will result in the inability to set the data cache enable area on the nu85e side.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 51 figure 2-5. data cache control register (dcc) (1/2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dcc 0 0 dc13 dc12 dc11 dc10 0000 dc05 dc04 00 dc01 dc00 address fffff078h initial value 0003h bit position bit name description this bit selects the cache lock setting of way 1 and clear or fill for the tag clear or tag fill function. setting (1) this bit locks the cache of way 1 and disables writing. dc13 cache lock tag clear/fill 0 way 1 is not locked way 1 tag clear function is valid 1 way 1 is locked way 1 tag fill function is valid 13 dc13 this bit selects the cache lock setting of way 0 and clear or fill for the tag clear or tag fill function. setting (1) this bit locks the cache of way 0 and disables writing. dc12 cache lock tag clear/fill 0 way 0 is not locked way 0 tag clear function is valid 1 way 0 is locked way 0 tag fill function is valid 12 dc12 these bits set the operating mode. dc11 dc10 operating mode 0 0 cache access disabled 1 0 write through mode 0 1 writeback mode (write allocate disabled) 1 1 writeback mode (write allocate enabled) 11, 10 dc11, dc10 remark write allocate refers to refilling the data cache with data of the address to be written from external memory when a miss occurs in writing to the data cache. 5 dc05 this bit sets a way 1 data flush. setting (1) this bit flushes a way 1 dirty data line. when a data flush is complete, this bit is cleared (0) automatically. 0: way 1 data flush complete 1: way 1 data flush operating
chapter 2 data cache preliminary user?s manual a15241ej2v0um 52 figure 2-5. data cache control register (dcc) (2/2) bit position bit name description 4 dc04 this bit sets a way 0 data flush. setting (1) this bit flushes a way 0 dirty data line. when a data flush is complete, this bit is cleared (0) automatically. 0: way 0 data flush complete 1: way 0 data flush operating this bit sets a way 1 tag clear or tag fill. setting (1) this bit clears or fills way 1 tags. when a tag clear or tag fill is complete, this bit is cleared (0) automatically. 0: way 1 tag clear or tag fill complete 1: way 1 tag clear or tag fill operating 1 dc01 remark select clear or fill using bit 13 (dc13). this bit sets a way 0 tag clear or tag fill. setting (1) this bit clears or fills way 0 tags. when a tag clear or tag fill is complete, this bit is cleared (0) automatically. 0: way 0 tag clear or tag fill complete 1: way 0 tag clear or tag fill operating 0 dc00 remark select clear or fill using bit 12 (dc12). (2) data cache data configuration register (dcd) the dcd register sets the address of the memory area to be tag filled when using the tag fill function. the dcd register can be read or written in 16-bit units. cautions 1. do not overwrite the dcd register while tag fill is operating. 2. since the initial value of the dcd register is undefined, when using the tag fill function, be sure to set a value in the dcd register prior to setting (1) the dc0n bit of the dcc register (n = 0, 1). if the dc0n bit of the dcc register is set (1) without setting a value in the dcd register, the operation cannot be guaranteed. figure 2-6. data cache data configuration register (dcd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dcd dd15 dd14 dd13 dd12 dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 address fffff07ch initial value undefined bit position bit name description 15 to 0 dd15 to dd0 these bits set tag information (bits 27 to 12 of the start address of the memory area to be tag filled).
chapter 2 data cache preliminary user?s manual a15241ej2v0um 53 2.4.2 tag clear function the tag clear function clears (invalidates) the tags of one or two ways. in addition, it automatically clears (invalidates) the tags of all ways on a reset. use the following procedure to perform a data cache tag clear. <1> read the data cache control register (dcc) and confirm that bits 0, 1, 4, and 5 (dc00, dc01, dc04, dc05) are all cleared (0). <2> clear (0) dcc register bit 12 (dc12), bit 13 (dc13), or both depending on the way for which tags are to be cleared. <3> set (1) dcc register bit 0 (dc00), bit 1 (dc01) or both depending on the way for which tags are to be cleared. <4> read dcc register bit dc00, dc01, or both depending on the way for which tags were cleared and confirm that that bit is cleared (0). caution the tag clear function does not flush dirty data lines even in writeback mode. if data flush is necessary, use the data flush function. 2.4.3 tag fill function the tag fill function fills the tags of one or two ways. by locking a filled way, the data cache can be used as data ram. when the lock is released, it again operates as a data cache. in write through mode, a bus cycle is issued even on a write access to a filled or locked address area. use the following procedure to perform a data cache tag fill. <1> set the tag information corresponding to the memory area to be tag filled in the data cache data configuration register (dcd). <2> read the data cache control register (dcc) and confirm that bits 0, 1, 4, and 5 (dc00, dc01, dc04, dc05) are all cleared (0). <3> set (1) dcc register bit 12 (dc12), bit 13 (dc13), or both depending on the way to be tag filled. <4> set (1) dcc register bit 0 (dc00), bit 1 (dc01), or both depending on the way to be tag filled. <5> read dcc register bit dc00, dc01, or both depending on the way that was tag filled and confirm that that bit is cleared (0). 2.4.4 lock function the lock function locks any way. once locked, a way is write disabled and operates the same as data ram that is accessible in one cycle. when the lock is released, it again operates as a data cache. in write through mode, a bus cycle is issued even on an access to a locked line. set or release a data cache lock as follows. ? setting a lock set (1) bit 12 (dc12) or bit 13 (dc13) of the data cache control register (dcc) depending on the way for which the lock is to be set. ? releasing a lock clear (0) bit dc12 or bit dc13 of the dcc register depending on the way for which the lock is to be released.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 54 2.4.5 data flush function the data flush function flushes a dirty data line in writeback mode. use the following procedure to perform a data cache data flush. <1> read the data cache control register (dcc) and confirm that bits 0, 1, 4, and 5 (dc00, dc01, dc04, dc05) are all cleared (0). <2> clear (0) dcc register bit 12 (dc12), bit 13 (dc13), or both depending on the way to be data flushed. <3> set (1) dcc register bit 4 (dc04), bit 5 (dc05), or both depending on the way to be data flushed. <4> read dcc register bit dc04, dc05, or both depending on the way that was data flushed and confirm that that bit is cleared (0). cautions 1. if bits dc04 and dc00 or bits dc05 and dc01 are set (1) at the same time, data flush and tag clear are performed at the same time. 2. when manipulating multiple ways simultaneously, make the settings the same. for example, a way 0 data flush and a way 1 data flush and tag clear cannot be performed simultaneously.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 55 2.5 data cache setting procedure 2.5.1 setting to validate data cache to validate the data cache, follow the procedure below using the initial settings of the user program immediately following system reset. <1> set the data cache control register (dcc) and data cache data configuration register (dcd) (always set the operating mode with bits dc11 and dc10 of the dcc register). <2> make the data cache setting of the cache configuration register (bhc) of the nu85e ?cacheable?. 2.5.2 setting to validate, invalidate, and revalidate data cache to invalidate (off) the data cache in the middle of a user program and validate (on) it again, use the data cache control register (dcc) or the cache configuration register (bhc) of the nu85e, and follow the procedure below. (1) using dcc register <1> read the dcc register and confirm that a tag clear is not in progress. <2> write 0x0 to the dcc register. <3> read the dcc register and confirm that the register is cleared (0). : : <4> read the dcc register and confirm that the register is cleared (0). <5> set the operating mode with bits 11 and 10 (dc11, dc10) of the dcc register. <6> nop (2) using bhc register of nu85e <1> make the data cache setting of the bhc register of the nu85e ?uncacheable?. <2> read the dcc register and confirm that a tag clear is not in progress. <3> set the tag clear bit of the dcc register. <4> read the dcc register and confirm that the tag clear is complete. : : <5> make the data cache setting of the bhc register of the nu85e ?cacheable?. caution do not perform other ld/st operations after bhc register write <1> and before tag clear completion using the dcc register <4>.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 56 2.6 operation the data cache automatically performs a caching operation whenever there is an access to a cacheable area set using the cache configuration register (bhc) of the nu85e. the data cache has three operating modes that are selected according to data cache control register (dcc) settings. table 2-2 shows a list of the operating modes. table 2-2. list of operating modes operating mode access type refill mode hit ? sequential read miss critical first hit ? write through mode write miss ? hit ? sequential clean data critical first sequential read miss dirty data critical first hit ? writeback mode (write allocate disabled) write miss ? hit ? sequential clean data critical first sequential read miss dirty data critical first hit ? sequential clean data critical first sequential writeback mode (write allocate enabled) write miss dirty data critical first data cache operation is described below for each operating mode.
chapter 2 data cache preliminary user?s manual a15241ej2v0um 57 2.6.1 write through mode (1) on a read (a) data cache hit <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the address existing in the data cache, read the data by passing through iramz31 to iramz0 from the data cache. figure 2-7. operation on data cache hit (write through mode, read) cpu data cache interface data cache <1> nu85e <2> iramz31 to iramz0 irama27 to irama2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 58 (b) data cache miss <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. <2> if a miss occurs due to the address not existing in the data cache, output a fetch request (iddrrq) and the address to be read (idea27 to idea0) from the data cache to the bcu. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) to external memory via the vsb and refills the data cache with one line (4 words) of data of the address to be read. <4> the data cache then transfers the required data among the 4 words of refill data to the cpu by passing through iramz31 to iramz0. figure 2-8. operation on data cache miss (write through mode, read) external memory cpu data cache interface bcu data cache vsb <1> nu85e <2> <3> <3> irama27 to irama2 iddrrq, idea27 to idea0 vbdi31 to vbdi0 vma27 to vma0 ided31 to ided0 memc dmac <4> iramz31 to iramz0 <3>
chapter 2 data cache preliminary user?s manual a15241ej2v0um 59 (2) on a write (a) data cache hit <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the external memory address to be written existing in the data cache, write the data to the data cache by passing through iraoz31 to iraoz0. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) to external memory via the vsb and writes the same data as iraoz31 to iraoz0 to external memory by passing through vbdo31 to vbdo0. figure 2-9. operation on data cache hit (write through mode, write) external memory cpu data cache interface bcu data cache vsb <1> nu85e <3> <3> irama27 to irama2 vbdo31 to vbdo0 vma27 to vma0 iraoz31 to iraoz0 memc dmac <2>
chapter 2 data cache preliminary user?s manual a15241ej2v0um 60 (b) data cache miss <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, data is not written to the data cache. <2> the bcu of the internal nu85e outputs the address (vma27 to vma0) to external memory via the vsb and writes the data to be written to external memory by passing through vbdo31 to vbdo0. figure 2-10. operation on data cache miss (write through mode, write) external memory cpu data cache interface bcu data cache vsb <1> nu85e <2> <2> irama27 to irama2 vbdo31 to vbdo0 vma27 to vma0 memc dmac
chapter 2 data cache preliminary user?s manual a15241ej2v0um 61 2.6.2 writeback mode (write allocate disabled) (1) on a read (a) data cache hit <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the address existing in the data cache, read the data by passing through iramz31 to iramz0 from the data cache. figure 2-11. operation on data cache hit (writeback mode, write allocate disabled, read) cpu data cache interface data cache <1> nu85e <2> iramz31 to iramz0 irama27 to irama2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 62 (b) data cache miss (i) when data being replaced is clean data <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, perform tag and data replacement. if the data being replaced is clean data, a write operation to external memory is not performed at this time. <2> the bcu of the internal nu85e outputs the address to be read (vma27 to vma0) to external memory via the vsb and refills the data cache with one line (4 words) of data of that address. <3> the data cache then transfers the required data among the 4 words of refill data to the cpu by passing through iramz31 to iramz0. figure 2-12. operation on data cache miss (writeback mode, write allocate disabled, read, clean data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <2> <2> irama27 to irama2 vbdi31 to vbdi0 dmac vma27 to vma0 <2> ided31 to ided0 <3> iramz31 to iramz0 memc
chapter 2 data cache preliminary user?s manual a15241ej2v0um 63 (ii) when data being replaced is dirty data <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, perform tag and data replacement. <2> if the data being replaced is dirty data, read the address corresponding to the line that has dirty data from the tag and output it in idea27 to idea0. at the same time, read the dirty data and output it in ided31 to ided0. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) of the dirty data to external memory via the vsb and writes one line (4 words) of the dirty data to be replaced to external memory. <4> it then outputs the address to be read (vma27 to vma0) to external memory and refills the data cache with 4 words of data of that address. <5> the data cache then transfers the required data among the 4 words of refill data to the cpu by passing through iramz31 to iramz0. figure 2-13. operation on data cache miss (writeback mode, write allocate disabled, read, dirty data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <3> <4> irama27 to irama2 vbdi31 to vbdi0 memc dmac idea27 to idea0, ided31 to ided0 <2> <4> ided31 to ided0 <5> iramz31 to iramz0 <4> vma27 to vma0 vma27 to vma0, vbdo31 to vbdo0
chapter 2 data cache preliminary user?s manual a15241ej2v0um 64 (2) on a write (a) data cache hit <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the external memory address to be written existing in the data cache, write the data to the data cache by passing through iraoz31 to iraoz0. figure 2-14. operation on data cache hit (writeback mode, write allocate disabled, write) cpu data cache interface data cache <1> nu85e <2> iraoz31 to iraoz0 irama27 to irama2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 65 (b) data cache miss <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, data is not written to the data cache. <2> the data cache outputs the address (irama27 to irama2) and data (iraoz31 to iraoz0) received from the cpu in idea27 to idea0 and ided31 to ided0, respectively. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) to external memory via the vsb and writes the data to be written to external memory by passing through vbdo31 to vbdo0. figure 2-15. operation on data cache miss (writeback mode, write allocate disabled, write) external memory cpu data cache interface bcu data cache vsb <1> nu85e <3> <3> irama27 to irama2 vbdo31 to vbdo0 vma27 to vma0 memc dmac iraoz31 to iraoz0 <2> idea27 to idea0, ided31 to ided0
chapter 2 data cache preliminary user?s manual a15241ej2v0um 66 2.6.3 writeback mode (write allocate enabled) (1) on a read (a) data cache hit <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the address existing in the data cache, read the data by passing through iramz31 to iramz0 from the data cache. figure 2-16. operation on data cache hit (writeback mode, write allocate enabled, read) cpu data cache interface data cache <1> nu85e <2> iramz31 to iramz0 irama27 to irama2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 67 (b) data cache miss (i) when data being replaced is clean data <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, perform tag and data replacement. if the data being replaced is clean data, a write operation to external memory is not performed at this time. <2> the bcu of the internal nu85e outputs the address to be read (vma27 to vma0) to external memory via the vsb and refills the data cache with one line (4 words) of data of that address. <3> the data cache then transfers the required data among the 4 words of refill data to the cpu by passing through iramz31 to iramz0. figure 2-17. operation on data cache miss (writeback mode, write allocate enabled, read, clean data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <2> <2> irama27 to irama2 vbdi31 to vbdi0 dmac vma27 to vma0 <2> ided31 to ided0 <3> iramz31 to iramz0 memc
chapter 2 data cache preliminary user?s manual a15241ej2v0um 68 (ii) when data being replaced is dirty data <1> when reading data from external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to the address not existing in the data cache, perform tag and data replacement. <2> if the data being replaced is dirty data, read the address corresponding to the line that has the dirty data from the tag and output it in idea27 to idea0. at the same time, read the dirty data and output it in ided31 to ided0. <3> the bcu of the internal nu85e outputs the address (vma27 to vma0) of the dirty data to external memory via the vsb and writes one line (4 words) of the dirty data to be replaced to external memory. <4> it then outputs the address to be read (vma27 to vma0) to external memory and refills the data cache with 4 words of data of that address. <5> the data cache then transfers the required data among the 4 words of refill data to the cpu by passing through iramz31 to iramz0. figure 2-18. operation on data cache miss (writeback mode, write allocate enabled, read, dirty data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <3> <4> irama27 to irama2 vbdi31 to vbdi0 memc dmac idea27 to idea0, ided31 to ided0 <2> <4> ided31 to ided0 <5> iramz31 to iramz0 <4> vma27 to vma0 vma27 to vma0, vbdo31 to vbdo0
chapter 2 data cache preliminary user?s manual a15241ej2v0um 69 (2) on a write (a) data cache hit <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. <2> if a hit occurs due to the external memory address to be written existing in the data cache, write the data to the data cache by passing through iraoz31 to iraoz0. figure 2-19. operation on data cache hit (writeback mode, write allocate enabled, write) cpu data cache interface data cache <1> nu85e <2> iraoz31 to iraoz0 irama27 to irama2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 70 (b) data cache miss (i) when data being replaced is clean data <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to that address not existing in the data cache, perform tag and data replacement. if the data being replaced is clean data, a write operation to external memory is not performed at this time. <2> the bcu of the internal nu85e outputs the address to be written (vma27 to vma0) to external memory via the vsb and refills the data cache with one line (4 words) of data of that address. <3> of the 4 words of refilled data, write the data of the address to be written to the data cache. figure 2-20. operation on data cache miss (writeback mode, write allocate enabled, write, clean data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <2> <2> irama27 to irama2 vbdi31 to vbdi0 dmac vma27 to vma0 <2> ided31 to ided0 <3> iraoz31 to iraoz0 memc
chapter 2 data cache preliminary user?s manual a15241ej2v0um 71 (ii) when data being replaced is dirty data <1> when writing data to external memory, output the address (irama27 to irama2) to the data cache. if a miss occurs due to that address not existing in the data cache, perform tag and data replacement. <2> if the data being replaced is dirty data, read the address corresponding to the line that has the dirty data from the tag and output it in idea27 to idea0. at the same time, read the dirty data and output it in ided31 to ided0. <3> the bcu in the internal nu85e outputs the address (vma27 to vma0) of the dirty data to external memory via the vsb and writes one line (4 words) of the dirty data to be replaced to external memory. <4> it then outputs the address to be written (vma27 to vma0) to external memory and refills the data cache with 4 words of data of that address. <5> of the 4 words of refilled data, write the data of the address to be written to the data cache. figure 2-21. operation on data cache miss (writeback mode, write allocate enabled, write, dirty data) external memory cpu data cache interface bcu data cache vsb <1> nu85e <3> <4> irama27 to irama2 vbdi31 to vbdi0 memc dmac idea27 to idea0, ided31 to ided0 <2> <4> ided31 to ided0 <5> iraoz31 to iraoz0 <4> vma27 to vma0 vma27 to vma0, vbdo31 to vbdo0
chapter 2 data cache preliminary user?s manual a15241ej2v0um 72 2.7 bus cycles issued by data cache the data cache issues the bus cycles shown in table 2-3 depending on the operating mode. figures 2-22 to 2-27 show timing examples in the case of a 32-bit data bus and a 16-bit data bus for each operating mode. the bus cycles indicated in figures 2-22 to 2-27 (a) 32-bit data bus are 4 times greater when an 8-bit data bus is used as a result of bus sizing. remarks 1. the timing example is when no waits are used. 2. all signals in the timing example are nu85e signals. 3. the circles indicate the sampling timing. 4. for details on the vsb signals (vmxxx, vdxxx), refer to the nu85e hardware user?s manual (a14874e) . 5. : undetermined state (for output), or arbitrary level (for input)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 73 table 2-3. operating modes and bus cycles operating mode access type refill mode bus cycle reference hit ? none ? sequential 4r figure 2-22 4r (irama3, irama2 = 00) ? 2r-2r (irama3, irama2 = 10) figure 2-23 read miss critical first 1r-2r-1r (irama2 = 1) figure 2-24 hit ? 1w ? wt write miss ? 1w ? hit ? none ? sequential 4r figure 2-22 4r (irama3, irama2 = 00) ? 2r-2r (irama3, irama2 = 10) figure 2-23 clean data critical first 1r-2r-1r (irama2 = 1) figure 2-24 sequential 4w + 4r figure 2-25 4w + 4r (irama3, irama2 = 00) ? 4w + 2r-2r (irama3, irama2 = 10) figure 2-26 read miss dirty data critical first 4w + 1r-2r-1r (irama2 = 1) figure 2-27 hit ? none ? wb write miss ? 1w ? hit ? none ? sequential 4r figure 2-22 4r (irama3, irama2 = 00) ? 2r-2r (irama3, irama2 = 10) figure 2-23 clean data critical first 1r-2r-1r (irama2 = 1) figure 2-24 sequential 4w + 4r figure 2-25 4w + 4r (irama3, irama2 = 00) ? 4w + 2r-2r (irama3, irama2 = 10) figure 2-26 wa read/write miss dirty data critical first 4w + 1r-2r-1r (irama2 = 1) figure 2-27 hit ? none ? read miss ? 1r (word access) ? hit (wt) ? 1w ? hit (wb, wa) ? none ? lock write miss ? 1w ? remarks 1. the meanings of the items in operating mode and access type columns are as follows. wt: write through mode wb: writeback mode (write allocate disabled) wa: writeback mode (write allocate enabled) 2. the meanings of the items in the bus cycle column are as follows. 1: single transfer 2: 2-word burst 4: 4-word burst r: read w: write
chapter 2 data cache preliminary user?s manual a15241ej2v0um 74 figure 2-22. sequential refill read cycle (4r) (1/2) (a) 32-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) (1,1) vmstz (output) adrs.+0h adrs.+4h adrs.+8h adrs.+ch (1,0) vmctyp2 to vmctyp0 (output) (0,0,1) vmbstr (output) vmbenz3 to vmbenz0 (output) (0,0,0,0) vmseq2 to vmseq0 (output) (0,1,0) (0,0,1) (0,0,0) vmlock (output) data.2 data.3 vmlast (input) vmahld (input) read data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 75 figure 2-22. sequential refill read cycle (4r) (2/2) (b) 16-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) vmstz (output) adrs.+0h adrs.+2h adrs.+4h adrs.+6h vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) (0,1,1) (0,0,0) vmlock (output) data.7 vmlast (input) vmahld (input) read adrs.+8h adrs.+ah adrs.+ch adrs.+eh data.6 (0,0,1) (1,1,0,0) (0,0,1) (1,0) (1,1) data.5 data.4 data.3 data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 76 figure 2-23. critical first refill read cycle (2r-2r) (1/2) (a) 32-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) (1,0) vmstz (output) adrs.+0h adrs.+4h adrs. ? 8h adrs. ? 4h (1,0) vmctyp2 to vmctyp0 (output) (0,0,1) vmbstr (output) vmbenz3 to vmbenz0 (output) (0,0,0,0) vmseq2 to vmseq0 (output) (0,0,1) (0,0,0) vmlock (output) data.2 data.3 vmlast (input) vmahld (input) (1,1) (1,1) (0,0,0) (0,0,1) read data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 77 figure 2-23. critical first refill read cycle (2r-2r) (2/2) (b) 16-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) vmstz (output) adrs.+0h adrs.+2h adrs.+4h adrs.+6h vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) (0,1,0) (0,0,0) vmlock (output) data.7 vmlast (input) vmahld (input) read adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h data.6 (0,0,1) (1,1,0,0) (0,0,1) (1,0) (1,1) (1,0) (1,1) (0,0,0) (0,1,0) (0,0,1) data.5 data.4 data.3 data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 78 figure 2-24. critical first refill read cycle (1r-2r-1r) (1/4) (a) 32-bit data bus (irama3, irama2 = 01) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) (1,1) vmstz (output) adrs.+0h adrs.+4h adrs.+8h adrs. ? 4h (1,0) vmctyp2 to vmctyp0 (output) (0,0,1) vmbstr (output) vmbenz3 to vmbenz0 (output) (0,0,0,0) vmseq2 to vmseq0 (output) (0,0,0) (0,0,0) vmlock (output) data.3 vmlast (input) vmahld (input) (1,0) (0,0,1) read data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 79 figure 2-24. critical first refill read cycle (1r-2r-1r) (2/4) (b) 32-bit data bus (irama3, irama2 = 11) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) (1,1) vmstz (output) adrs.+0h adrs. ? ch adrs. ? 8h adrs. ? 4h (1,0) vmctyp2 to vmctyp0 (output) (0,0,1) vmbstr (output) vmbenz3 to vmbenz0 (output) (0,0,0,0) vmseq2 to vmseq0 (output) (0,0,0) (0,0,0) vmlock (output) data.3 vmlast (input) vmahld (input) (1,0) (0,0,1) read data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 80 figure 2-24. critical first refill read cycle (1r-2r-1r) (3/4) (c) 16-bit data bus (irama3, irama2 = 01) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) vmstz (output) adrs.+0h adrs.+2h adrs.+4h adrs.+6h vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) (0,0,1) (0,0,0) vmlock (output) data.7 vmlast (input) vmahld (input) read adrs.+8h adrs.+ah adrs. ? 4h adrs. ? 2h data.6 (1,1,0,0) (0,0,1) (1,0) (1,0) (1,1) (0,0,0) (0,1,0) (0,0,1) (0,0,1) (0,0,0) (1,1) (1,0) (1,1) data.5 data.4 data.3 data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 81 figure 2-24. critical first refill read cycle (1r-2r-1r) (4/4) (d) 16-bit data bus (irama3, irama2 = 11) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vbclk (input) (1,0) vmstz (output) adrs.+0h adrs.+2h adrs. ? ch adrs. ? ah vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) (0,0,1) (0,0,0) vmlock (output) data.7 vmlast (input) vmahld (input) read adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h data.6 (1,1,0,0) (0,0,1) (1,0) (1,0) (1,1) (0,0,0) (0,1,0) (0,0,1) (0,0,1) (0,0,0) (1,1) (1,0) (1,1) data.5 data.4 data.3 data.2 data.1 data.0 vbdo31 to vbdo0 (output) l
chapter 2 data cache preliminary user?s manual a15241ej2v0um 82 figure 2-25. sequential refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 4r) (1/2) (a) 32-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (1,1) (1,0) adrs.+0h adrs.+4h adrs.+ch adrs.+0h adrs.+4h adrs.+8h adrs.+ch (0,1,0) (0,0,1) (0,0,0) (0,1,0) (0,0,1) (0,0,0) data.1 data.2 read data.0 write (0,0,0,0) (0,0,1) (1,0) (0,0,1) (1,0) (0,0,0,0) data.3 vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3 adrs.+8h
chapter 2 data cache preliminary user?s manual a15241ej2v0um 83 figure 2-25. sequential refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 4r) (2/2) (b) 16-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (1,0) adrs.+0h adrs.+2h adrs.+4h adrs.+6h adrs.+0h adrs.+2h adrs.+4h adrs.+6h (0,1,1) (0,1,1) data.1 data.2 read write data.3 adrs.+8h adrs.+ah adrs.+ch adrs.+eh (1,0) (0,0,0) (1,1,0,0) (0,0,1) adrs.+8h adrs.+ah adrs.+ch adrs.+eh (0,0,0) data.6 data.7 data.4 data.5 (1,1) (1,0) (0,0,1) (1,1,0,0) (0,0,1) (0,0,1) data.0 vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3 data.4 data.5 data.6 data.7
chapter 2 data cache preliminary user?s manual a15241ej2v0um 84 figure 2-26. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 2r-2r) (1/2) (a) 32-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (1,0) adrs. ? 8h adrs. ? 4h adrs.+0h adrs.+4h adrs.+0h adrs.+4h adrs. ? 8h adrs. ? 4h (0,1,0) (0,0,1) (0,0,0) (0,0,1) (0,0,0) (0,0,0) data.1 data.2 (1,1) (1,0) (1,1) (0,0,1) read write (0,0,0,0) (0,0,1) (1,0) (0,0,0,0) (0,0,1) (1,0) data.3 data.0 vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3
chapter 2 data cache preliminary user?s manual a15241ej2v0um 85 figure 2-26. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 2r-2r) (2/2) (b) 16-bit data bus vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) (1,1) (1,0) adrs.+0h adrs.+2h adrs.+4h adrs.+6h (0,1,0) (0,0,1) (0,0,0) read write (1,1) (1,0) adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h (0,1,0) (0,0,1) (0,0,0) (0,0,1) (1,0) (1,1,0,0) (1,1) (1,0) adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h (0,1,1) data.1 data.2 data.3 adrs.+0h adrs.+2h adrs.+4h adrs.+6h (1,0) (0,0,0) (1,1,0,0) (0,0,1) data.6 data.7 data.4 data.5 (0,0,1) data.0 vbclk (input) vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3 data.4 data.5 data.6 data.7
chapter 2 data cache preliminary user?s manual a15241ej2v0um 86 figure 2-27. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 1r-2r-1r) (1/4) (a) 32-bit data bus (irama3, irama2 = 01) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (1,0) adrs. ? 4h adrs.+0h adrs.+4h adrs.+8h adrs.+0h adrs.+4h adrs.+8h adrs. ? 4h (0,1,0) (0,0,1) (0,0,0) (0,0,0) (0,0,1) (0,0,0) data.1 data.2 (1,1) (1,0) write read (0,0,0,0) (0,0,1) (1,0) (0,0,0,0) (0,0,1) (1,0) data.3 data.0 vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3
chapter 2 data cache preliminary user?s manual a15241ej2v0um 87 figure 2-27. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 1r-2r-1r) (2/4) (b) 32-bit data bus (irama3, irama2 = 11) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (1,0) adrs. ? ch adrs. ? 8h adrs. ? 4h adrs.+0h adrs.+0h adrs. ? ch adrs. ? 8h adrs. ? 4h (0,1,0) (0,0,1) (0,0,0) (0,0,0) (0,0,1) (0,0,0) data.1 data.2 (1,1) (1,0) write read (0,0,0,0) (0,0,1) (1,0) (0,0,0,0) (0,0,1) (1,0) data.3 data.0 vbdo31 to vbdo0 (output) data.0 data.1 data.2 data.3
chapter 2 data cache preliminary user?s manual a15241ej2v0um 88 figure 2-27. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 1r-2r-1r) (3/4) (c) 16-bit data bus (irama3, irama2 = 01) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (0,0,1) (0,0,0) read write (1,0) (0,1,0) (0,0,1) (0,0,0) (0,0,1) (1,0) (1,1,0,0) (1,1) (1,0) (0,1,1) data.1 data.2 data.3 (1,0) (0,0,0) (1,1,0,0) (0,0,1) data.6 data.7 data.4 data.5 (0,0,1) (1,1) (1,0) (1,1) (0,0,1) (0,0,0) data.0 adrs. ? 4h adrs. ? 2h adrs.+0h adrs.+2h adrs.+4h adrs.+6h adrs.+8h adrs.+ah adrs.+0h adrs.+2h adrs.+4h adrs.+6h adrs.+8h adrs.+ah adrs. ? 4h adrs. ? 2h vbdo31 to vbdo0 (output) data.3 data.4 data.5 data.6 data.7 data.0 data.1 data.2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 89 figure 2-27. critical first refill read cycle in writeback mode (when data being replaced is dirty data) (4w + 1r-2r-1r) (4/4) (d) 16-bit data bus (irama3, irama2 = 11) vmttyp1, vmttyp0 (output) vma27 to vma0 (output) vmwrite (output) vdselpz (output) vmwait (input) vbdi31 to vbdi0 (input) vdcsz7 to vdcsz0 (output) vmsize1, vmsize0 (output) vbdc (output) vmstz (output) vmctyp2 to vmctyp0 (output) vmbstr (output) vmbenz3 to vmbenz0 (output) vmseq2 to vmseq0 (output) vmlock (output) vmlast (input) vmahld (input) vbclk (input) (1,1) (1,0) (0,0,1) (0,0,0) read write (1,0) (0,1,0) (0,0,1) (0,0,0) (0,0,1) (1,0) (1,1,0,0) (1,1) (1,0) (0,1,1) data.1 data.2 data.3 (1,0) (0,0,0) (1,1,0,0) (0,0,1) data.6 data.7 data.4 data.5 (0,0,1) (1,1) (1,0) (1,1) (0,0,1) (0,0,0) data.0 adrs. ? ch adrs. ? ah adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h adrs.+0h adrs.+2h adrs.+0h adrs.+2h adrs. ? ch adrs. ? ah adrs. ? 8h adrs. ? 6h adrs. ? 4h adrs. ? 2h vbdo31 to vbdo0 (output) data.3 data.4 data.5 data.6 data.7 data.0 data.1 data.2
chapter 2 data cache preliminary user?s manual a15241ej2v0um 90 2.8 timing of refill from sdram to data cache figures 2-28 to 2-30 show the refill timing examples from sdram to the data cache for each refill mode. remarks 1. these timing examples assume the following conditions. ? 32-bit data bus ? cas latency = 2 ? number of wait states set with bits bcw1, bcw0 of sdram configuration register n (scrn) of the sdram controller (nt85e502) = 1 (n = 7 to 0) 2. the circles indicate the sampling timing. 3. for details on the vsb signals (vmxxx), refer to the nu85e hardware user?s manual (a14874e) . 4. the inputs and outputs as seen from the memory controller (memc) side are shown. 5. the various state abbreviations have the following meanings. tw: wait state tact: bank active command state tread: read command state tlate: latency wait state 6. : undetermined state (for output), or arbitrary level (for input)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 91 figure 2-28. refill timing example from sdram to data cache (sequential refill (4r), critical first refill (4r)) note nu85e signal. this signal is not connected to memc. 4-word read vba25 to vba0 (input) tw vbclk (input) vbdi31 to vbdi0 (output) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vmsize1, vmsize0 (output) note sdwez (output) di31 to di0 (input) tact tread tread tread tlate tlate tread between nu85e and memc between memc and sdram (1,0) (0,0,0,0) (0,1,0) (0,0,1) (0,0,0) vmlock (output) note a22 to a13 (output) a24, a23 (output) adrs. bank a12 (output) adrs. row a11 to a2 (output) adrs. row col. col. sdrasz (output) sdcasz (output) h hi-z adrs.+ch col. col. hi-z adrs.+8h adrs.+4h adrs.+ch adrs.+8h adrs.+4h adrs.+ch adrs.+8h adrs.+4h adrs.+0h adrs.+0h adrs.+0h
chapter 2 data cache preliminary user?s manual a15241ej2v0um 92 figure 2-29. refill timing example from sdram to data cache (critical first refill (2r-2r)) note nu85e signal. this signal is not connected to memc. vba25 to vba0 (input) tw vbclk (input) vbdi31 to vbdi0 (output) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vmsize1, vmsize0 (output) note sdwez (output) di31 to di0 (input) tact tread tlate tlate tread tlate tlate tw tread tread between nu85e and memc between memc and sdram (1,0) adrs. ? 8h 2-word read 2-word read (0,0,0,0) (0,0,1) (0,0,0) (0,0,1) vmlock (output) note a22 to a13 (output) adrs. ? 8h a24, a23 (output) adrs. bank a12 (output) adrs. row a11 to a2 (output) adrs. row col. col. col. sdrasz (output) sdcasz (output) h hi-z hi-z adrs. ? 8h (0,0,0) col. hi-z adrs.+0h adrs.+0h adrs.+0h adrs. ? 4h adrs. ? 4h adrs. ? 4h adrs.+4h adrs.+4h adrs.+4h
chapter 2 data cache preliminary user?s manual a15241ej2v0um 93 remark this is an example when irama3, irama2 = 01. figure 2-30. refill timing example from sdram to data cache (critical first refill (1r-2r-1r)) note nu85e signal. this signal is not connected to memc. vba25 to vba0 (input) tw vbclk (input) vbdi31 to vbdi0 (output) vbbenz3 to vbbenz0 (input) vbseq2 to vbseq0 (input) vmsize1, vmsize0 (output) note sdwez (output) di31 to di0 (input) tact tread tlate tlate tw tread tlate tlate tw tread tread tlate tlate between nu85e and memc between memc and sdram (1,0) adrs.+4h 1-word read 2-word read 1-word read adrs. ? 4h (0,0,0,0) (0,0,0) (0,0,1) (0,0,0) vmlock (output) note a22 to a13 (output) adrs.+4h adrs. ? 4h a24, a23 (output) adrs. bank a12 (output) adrs. row a11 to a2 (output) adrs. row col. col. col. col. sdrasz (output) sdcasz (output) h hi-z hi-z hi-z adrs. ? 4h adrs.+4h hi-z adrs.+8h adrs.+0h adrs.+0h adrs.+0h adrs.+8h adrs.+8h
chapter 2 data cache preliminary user?s manual a15241ej2v0um 94 2.9 refill sequence to data cache the refill sequence to the data part of a data cache when a miss occurs differs depending on the refill mode. figures 2-31 to 2-33 show the refill sequence for each refill mode. figure 2-31. refill sequence to data cache (sequential refill (4r), critical first refill (4r)) (a) 32-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <1> (adrs.+0h) <3> (adrs.+8h) <2> (adrs.+4h) <4> (adrs.+ch) higher address lower address (b) 16-bit data bus <8> (adrs.+eh) <7> (adrs.+ch) <6> (adrs.+ah) <5> (adrs.+8h) <4> (adrs.+6h) <3> (adrs.+4h) <2> (adrs.+2h) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <1> (adrs.+0h) higher address lower address (c) 8-bit data bus <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <5> <6> <3> <4> <1> <2> ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address (adrs.+fh) (adrs.+eh) (adrs.+dh) (adrs.+ch) (adrs.+ah) (adrs.+6h) (adrs.+8h) (adrs.+4h) (adrs.+2h) (adrs.+0h) (adrs.+7h) (adrs.+9h) (adrs.+bh) (adrs.+5h) (adrs.+3h) (adrs.+1h) remarks 1. the numbers within pointed brackets (< >) indicate the refill sequence. 2. (adrs.+n): data of address in ( ) (n = 0h to fh)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 95 figure 2-32. refill sequence to data cache (critical first refill (2r-2r)) (a) 32-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <3> (adrs. ? 8h) <1> (adrs.+0h) <4> (adrs. ? 4h) <2> (adrs.+4h) higher address lower address (b) 16-bit data bus <4> (adrs.+6h) <3> (adrs.+4h) <2> (adrs.+2h) <1> (adrs.+0h) <8> (adrs. ? 2h) <7> (adrs. ? 4h) <6> (adrs. ? 6h) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <5> (adrs. ? 8h) higher address lower address (c) 8-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address <9> <10> <11> <12> <13> <14> <15> <16> (adrs. ? 1h) (adrs. ? 2h) (adrs. ? 3h) (adrs. ? 4h) (adrs. ? 6h) (adrs. ? 8h) (adrs. ? 7h) (adrs. ? 5h) <7> <8> <5> <6> <3> <4> <1> <2> (adrs.+6h) (adrs.+4h) (adrs.+2h) (adrs.+0h) (adrs.+7h) (adrs.+5h) (adrs.+3h) (adrs.+1h) remarks 1. the numbers within pointed brackets (< >) indicate the refill sequence. 2. (adrs.+n): data of address in ( ) (n = ? 8h to +7h)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 96 figure 2-33. refill sequence to data cache (critical first refill (1r-2r-1r)) (1/2) (1) irama3, irama2 = 01 (a) 32-bit data bus <3> (adrs.+8h) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <1> (adrs.+0h) <4> (adrs. ? 4h) <2> (adrs.+4h) higher address lower address (b) 16-bit data bus <6> (adrs.+ah) <5> (adrs.+8h) <4> (adrs.+6h) <3> (adrs.+4h) <2> (adrs.+2h) <1> (adrs.+0h) <8> (adrs. ? 2h) <7> (adrs. ? 4h) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address (c) 8-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address <7> <8> <5> <6> <3> <4> <1> <2> (adrs.+6h) (adrs.+4h) (adrs.+2h) (adrs.+0h) (adrs.+7h) (adrs.+5h) (adrs.+3h) (adrs.+1h) <9> <10> <11> <12> (adrs.+ah) (adrs.+8h) (adrs.+9h) (adrs.+bh) <13> <14> <15> <16> (adrs. ? 1h) (adrs. ? 2h) (adrs. ? 3h) (adrs. ? 4h) remarks 1. the numbers within pointed brackets (< >) indicate the refill sequence. 2. (adrs.+n): data of address in ( ) (n = ? 4h to +bh)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 97 figure 2-33. refill sequence to data cache (critical first refill (1r-2r-1r)) (2/2) (2) irama3, irama2 = 11 (a) 32-bit data bus <3> (adrs. ? 8h) <2> (adrs. ? ch) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries <1> (adrs.+0h) <4> (adrs. ? 4h) higher address lower address (b) 16-bit data bus <2> (adrs.+2h) <1> (adrs.+0h) <8> (adrs. ? 2h) <7> (adrs. ? 4h) <6> (adrs. ? 6h) <5> (adrs. ? 8h) <4> (adrs. ? ah) <3> (adrs. ? ch) ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address (c) 8-bit data bus ? ? ? ? ? ? ? ? ? 1 word 1 word 1 word 1 word data part (4 words) 256 entries higher address lower address <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <5> <6> (adrs. ? 1h) (adrs. ? 2h) (adrs. ? 3h) (adrs. ? 4h) (adrs. ? 6h) (adrs. ? ah) (adrs. ? 8h) (adrs. ? ch) (adrs. ? 9h) (adrs. ? 7h) (adrs. ? 5h) (adrs. ? bh) <3> <4> <1> <2> (adrs.+2h) (adrs.+0h) (adrs.+3h) (adrs.+1h) remarks 1. the numbers within pointed brackets (< >) indicate the refill sequence. 2. (adrs.+n): data of address in ( ) (n = ? ch to +3h)
chapter 2 data cache preliminary user?s manual a15241ej2v0um 98 2.10 cautions (1) connection to nu85e connect pins that have the same pin names. however, the following pins should be connected as follows (connect to pins that do not have the same pin names). vpdr15 to vpdr0: connect to the vpdi15 to vpdi0 pins of the nu85e. vpdw15 to vpdw0: connect to the vpdo15 to vpdo0 pins of the nu85e. bunriin: connect to the bunriout pin of the nu85e. (2) setting cache type selection pins input the levels shown below to cache type selection pins beginning with ifi. however, connect the ifiunch1 pin and the ifiwrth pin to the nu85e. input level pin name nu85e252 nu85e263 ifiaseq don?t care don?t care ifirabe low level low level ifidrct note ? low level note nu85e263 only (3) bus cycle status for all read cycles of an area for which the data cache setting is set to cacheable by the cache configuration register (bhc) of the nu85e and write cycles in writeback mode (write allocate enabled), the vmctyp2 to vmctyp0 signals of the nu85e always indicate a data access and do not indicate a misalign access. (4) operation on reset at the time of a reset, tags are automatically cleared (invalidated), which puts the next data replacement in a state of being performed from way 0. therefore, if there is an access to the data cache within a period of as many clock cycles as the number of lines after a reset, the cpu stops until the tags are cleared (become invalid). (5) other this data cache does not have a bus snoop circuit (which monitors the bus operation). note that data in the data cache in the cases shown in the following examples is dirty data even when there is no write access to the data cache, and is data that has lost its coherency. to avoid this status, be sure to clear tags. examples 1. when dma transfer is performed to the external memory of a cacheable area (transfer data is not reflected in the data cache) 2. when the external memory contents of a cacheable area are overwritten by the external bus master (6) operation during debugging this data cache does not operate during debugging using an n-wire type in-circuit emulator. when accessing external memory in the cacheable area during debugging, only the external memory is accessed even if the data cache is valid, and data loses its coherency. to avoid this, be sure to clear tags.
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